1. Technical Domain
The present invention concerns the domain of microelectronics and more specifically, that of interconnection elements within an integrated circuit.
2. Prior Art
The electrical connections between two different plans of an integrated circuit are conventionally implemented through via holes. A via hole can be considered as a hole traversing an insulation layer separating a lower conductive layer and an upper conductive layer, this hole being filled with a metal, typically copper, to ensure the electrical connection between both layers.
This type of connection is satisfactory for micrometric interconnection means. However, for designs with smaller lateral dimensions, there is the constraint of utilizing via holes of diameter less than 100 nm or even 50 nm. The height/diameter ratio of the hole thus becomes high, making the metallic deposit particularly delicate due to the fact that the hole in question is prone to partial blockage in its upper section before eventually becoming completely filled. In addition, the smaller the diameter of the via hole, the more sensitive the electromigration phenomena become, thereby reducing both the maximum current that can be flown and the lifespan of the connection. Finally, the reduction in the diameter of the via holes results in an increased interconnection resistance, which reduces the maximum functional speed of the integrated circuit by the same extent.
To overcome the aforementioned drawbacks, it was proposed to replace the metal via holes by an array of carbon nanotubes. Due to their excellent conductive properties, and their mechanical and thermal stability, carbon nanotubes are indeed well suited for use for via holes of very small dimensions. Such a via hole is described, for example, in the WO 01/61753 application.
FIG. 1 illustrates a via hole using nanotubes known in the art. For reasons of simplification, the substrate has not been shown.
The via hole provides the connection between a lower conductor 110 and an upper conductor 120, separated by a dielectric layer 130. The hole 140 contains carbon nanotubes (CNT) 150, extending from the lower conductor to the upper conductor.
The CNT are made via catalytic synthesis. More precisely, a catalyst (typically using nickel nanoparticles) is deposited on the lower conductor in order to initiate the CNT formation during a chemical deposition phase in a vapour phase (CVD). The CNT subsequently grows from the lower conductor to the upper conductor. The catalyst deposit must be localised in the bottom of the via hole. By contrast, if a catalyst is deposited on the walls of the hole, this enhances the lateral growth of CNT, which disrupts or even prevents the growth of the vertical array, the only effective participant in the electrical connection between the lower and upper conductors. Preventing deposition on the walls of the hole is even more vital when the diameter is small.
In order to avoid parasitic lateral growth of the CNT, it was proposed in the article by F. Kreupl entitled “Carbon Nanotubes for Interconnect Applications” published in Microelectron. Eng. 64, pages 399-408, 2002, to initially proceed with the deposition of a catalyst on the lower conductor before proceeding with the deposition of the dielectric layer. The hole is subsequently etched up to the catalyst area before causing the CNT to grow. Implementing this technique is very delicate, since it requires the etching process to be stopped on a catalyst layer with a thickness of several nanometers. Moreover, the physicochemical properties of the catalyst layer may be impacted by the phases of deposition and etching of the dielectric layer, and its catalytic activity may consequently be significantly affected.
Whatever the mode of catalyst deposition selected, it involves making the CNT grow from the lower conductor, and generally speaking, the next step involves proceeding to chemical mechanical planarisation (CMP). The upper conductor is subsequently deposited on the planarised surface.
The main difficulty arising with this technique is obtaining ohmic contact between the CNT and the lower and upper conductors. The deposition of the upper conductor is performed at a relatively low temperature and annealing would burden the thermal budget of the integrated circuit.
A first object of the present invention is to realise a carbon nanotube-based interconnection element presenting good electrical contact between the nanotubes and the conductors to be interconnected.
A second object of the present invention is to limit or significantly reduce the lateral growth of the CNT without risking to damage to catalyst layer.
A third object of the present invention is to get rid of the polishing step after the growth of the carbon nanotubes.